The present invention relates to a device for shunting and recovering data.
An information system is generally provided with an interrupting function for changing the processing condition of a central processor based upon such interruption sources as a request from the outside of the central processor, a condition generated within the central processor, and a condition generated in an input/output device.
When an interrupt is generated, the central processor suspends the program which has been executed up to that time, and executes the interrupt processing program. This shift from the suspended instruction to the interrupt processing program is done through change of the program status word (PSW) which decides the operation of the central processor. When the processing of the interrupt processing program terminates, the central processor should return to the program which was executed prior to the generation of the interrupt. For this purpose, it is required to load a correct PSW at the time of generation of the interrupt for indicating the address of an instruction word which is to be subsequently processed.
The PSW includes eight bytes or so indicative of control information of programs executed by the central processor such as an instruction address, an instruction length code, a condition code, a memory protection key, an interruption code indicating the interruption source, and an interrupt mask indicating whether the generation of such interrupt is permitted or not. When an interrupt is generated, the PSW for the program which has been executed up to that time (hereinafter referred to as old PSW) is stored in a predetermined address of the main storage, and there is subsequently read out of a predetermined address of the main storage a PSW specifying the control information of the interrupt processing program (hereinafter referred to as new PSW). The execution of the interrupt processing program starts according to the instruction in the main storage stored at an instruction address specified by the new PSW.
When the interrupt is generated, the instruction which is being executed performs one of the following types of end operation in accordance with the existing interruption source: (1) Completion, (2) Nullification, (3) Suppression, and (4) Termination.
In the completion-type end operation, even when an interruption source is generated, the instruction is normally completed, the result obtained is stored in an operand address indicated by the instruction, and the condition code is renewed. The instruction address in the old PSW which is stored in the predetermined address of the main storage indicates an instruction which is to be subsequently executed.
In the nullification-type and the suppression-type interruption, the interruption source is detected immediately before the instruction is started so that the interrupted instruction is not executed at all. That is, the operand and the condition code given by the interrupted instruction are maintained as they were before the instruction is executed. However, the instruction address in the old PSW is set in different manners between the nullification-type and suppression-type end operations. That is, in the nullification-type end operation, the instruction address in the old PSW is set to designate the interrupted instruction itself, while, in the suppression-type end operation, the instruction address is set to designate an instruction which is to be executed subsequently to the interrupted instruction.
In the termination-type end operation, the execution of instruction is suspended at the time when an interruption source is generated. Thus, it is not possible to anticipate the state of operand and the condition code which are specified by the instruction. The instruction address in the old PSW indicates the address of an instruction which is to be executed subsequently to the interrupted instruction.
The foregoing description shows the manner in which the interrupt function is normally conducted in a typical information processing apparatus. Although there are many information processing apparatuses in which the interrupt is processed in different manners from the above-mentioned, all the information processing apparatuses are the same in that the interrupted instruction ends according to the aforementioned types of end operation such as the completion, nullification, supression and termination types. Therefore, the present invention is applicable to any information processing apparatus irrespective of how the interrupt is carried out.
As is well-known, a central processor is connected with a main storage which is further connected with another central processor or with a plurality of input/output channels. In general, the central processor includes an instruction unit (I unit), an execution unit (E unit), a buffer storage, an address translation table, and further includes a storage control unit (S unit) which is connected with the main storage. In the central processor, the instruction unit reads an instruction out of the storage control unit, and produces various kinds of operand data and control signals which are communicated to the execution unit in order that the execution unit can perform the processing specified by the instruction. The execution unit performs according to the operand data prepared by the instruction unit such operations as arithmetic operation, logical operation, character shift and processing of control information in the processor, and then stores the results of operations in the register, storage, or the like which is specified by the instruction.
Each instruction is processed at five stages of D, A, L, E and P in a manner as mentioned below. The operation at each stage terminates in a machine cycle which is defined in the central processor.
Now, let us suppose a fundamental processing of an addition instruction by which the operand data in the storage and contents of a general purpose register included in the processor are added and the result of addition is stored in the general purpose register. First, the instruction unit reads out of the storing control unit an instruction which is to be subsequently executed. Then, in order to determine the operand address in the storage, there are added at the D stage (decode) the contents of a base register specified by the instruction word, the contents of an index register, and a displacement. Thus, the operand address is obtained. At the A stage (association), the operand address obtained at the D stage is sent to the storage control unit, and the storage control unit indexes an address translation management table and a buffer memory management table to obtain a buffer memory address by which a buffer memory can be accessed. At the L stage (load), the operand data is read out of the buffer memory in the storage control unit, and transferred to the execution unit. The instruction unit reads out the contents of the general purpose register which are another operand of the instruction according to a register address specified by the instruction word, and transfers the read contents of the execution unit. Thus, the execution unit includes on the termination of the L stage the operand data necessary for the operation specified by the instruction. When the instruction advances to the L stage and the necessary operand data and control information are given to the execution unit, the subsequent processing of the instruction relies on the execution unit. After receiving the operand data, the execution unit finishes the execution of instruction in two cycles of the E and P stages (execution and put-away). That is, at the E stage, the register operand and the operand on the storage are added. At the P stage, the result of addition is stored in the general purpose register specified by the instruction. Thus, the execution of instruction terminates.
Even if the instruction specifies that the result of operation is stored in the storage and in a register of another processor or is stored as the condition code, the resultant operands are all stored at the P stage.
In the foregoing description, the processing of a single instruction is performed at the five stages of D, A, L, E, and P. However, those processors in which a high speed processing is required, are constructed in such a manner that the respective stages can be independently operated. For example, in the E unit, the operand address of an instruction is obtained in a certain cycle, and the operand address of the succeeding instruction can be obtained in the next cycle. This is called the pipe-line control. In such a control, the successive instructions terminate successively with a one cycle shift, though five cycles are required for processing of each instruction.
The processing performance in the pipe-line control can be seen from a simplified stage flow shown in Table 1.
TABLE 1 ______________________________________ CYCLE t.sub.0 t.sub.1 t.sub.2 t.sub.3 t.sub.4 t.sub.5 t.sub.6 ______________________________________ STAGE D a b c d e e f A a b c d d e L a b c c d E a b b c P a b ______________________________________
Table 1 shows a manner in which six instructions a, b, c, d, e and f are carried out. In a cycle t.sub.0, the D stage operation of instruction a is performed, so that the operand address is defined. In a cycle t.sub.1, the instruction a is shifted to the A stage where the buffer memory address is obtained in the storage control unit. The instruction a is shifted to the L stage in a cycle t.sub.2, to the E stage in a cycle t.sub.3, and to the P stage in a cycle t.sub.4. Thus, the processing of the instruction a is completed in a period from t.sub.0 to t.sub.4. In the cycle t.sub.1 when the instruction a is shifted to the A stage, the D stage processes the succeeding instruction b. In the cycle t.sub.2, the A and D stages process the instructions b and c, respectively. Further, according to Table 1, it is shown at the E stage in cycles t.sub.4 and t.sub.5 that the operation of the instruction b at the E stage is not completed in one cycle, but requires two cycles. Such a situation takes place for an instruction of which an operation can not be completed in one cycle, such as an instruction indicating multiplication/division, or the like. In such a case, the instructions subsequent to the instruction b are, as shown in Table 1, maintained at the same stage for two cycles, because of the occupation of the E stage by the instruction b for two cycles. In the foregoing, there has been shown the general operation of the pipe-line control.
When the previously-mentioned interruption sources are generated in a processor which is controlled in the pipe-line control mode, the operand specified by the instruction has to be maintained in a stage existing prior to the execution of the instruction in the nullification-type or suppression-type interrupt. If an interrupt of such a type is generated in an addition instruction, the additive operation at the E stage is allowed, but either the condition code or the general purpose registers should not be renewed at the P stage. In the completion-type interrupt, the processing at the P stage is allowed since the instruction is normally completed, but the processing at the P stage of the succeeding instruction is inhibited.
If the suppression-type or nullification-type interrupt is generated when the instruction a exists in the cycle t.sub.3, the processing at the P stage which is allotted to write the result of operation of the instruction a into the condition code, registers, or the main storage should be inhibited because the operating result is inhibited from being stored in the operand specified by the instruction a according to the type of the interrupt. In other words, the instruction a which has stayed at the D stage in the cycle t.sub.0 advances to the A stage in the cycle t.sub.1, to the L stage in the cycle t.sub.2, and to the E stage in the cycle t.sub.3. However, it is required to stop the pipe-line control so as to stop the storage of the result of operation to the specified operand before the operation advances to the cycle t.sub.4. That is, the advance of stages has to be stopped before the pipe-line control advances beyond the cycle t.sub.3. Further, in a case that the completion-type interrupt is generated when the instruction a exists in the cycle t.sub.4, the advance of stages has to be stopped in the cycle t.sub. 4 since it is necessary to stop the pipe-line control prior to the processing of the instruction b at the P stage.
In the termination-type interrupt in which it is not necessary to maintain the contents of the operand specified by the instruction, either one of the above-mentioned stopping methods may be selected in accordance with the interruption sources. The above-mentioned operation is described, in detail, in "Computing Surveys" Vol. 9, No. 1, the Association for Computing Machinery Inc., pages 61-102 "Pipeline Architecture" by C. V. Ramamoothy and H. F. Li.
When a high-speed operation is desired for processors, it is necessary to reduce the number of computing cycles in an arithmetic unit as well as operating in the aforementioned pipe-line control mode. All instructions prepared in a processor can be processed by a fundamental arithmetic unit which includes a set of main adders, a set of shifters, a set of byte adders, and several work registers. However, in a case that such a fundamental arithmethic unit executes, for example, an instruction indicating multiplication/division or an instruction indicating the processing of floating-point operands, such an instruction will occupy a period of several to several tens cycles the main adders, shifters, or the like. However, such an instruction as employing the fundamental arithmetic unit for a long time will be executed with a reduced number of computing cycles, and thus the processing speed of the instruction will be improved, if a multiplier/divider or a floating-point adder/subtracter is incorporated to the fundamental arithmetic unit. In such a case, the execution unit is divided into two units, i.e. a floating and high speed arithmetic unit which is equipped with the multiplier/divider and the floating-point adder/subtractor for executing an instruction indicating multiplication/division and an instruction indicating floating-point arithmetic, respectively, and a general arithmetic unit which includes the main adders, shifters and/or byte adders for performing other operations than the operations executed by the floating and high speed arithmetic unit. Each of the arithmetic units is connected with the I unit, and therefore can receive from the instruction unit the operand data and control information required for its operation. Further, the arithmetic units are connected with the storage unit unit to store the results of their operations in the main storage.
However, if the execution unit is, as mentioned above, divided into the two units to reduce the number of computing cycles, a bulky hardware is required for each of the arithmetic units. Therefore, the two units cannot be placed in adjacent packaged regions. Further, when the packaged regions for the arithmetic units become large in volume, the physical distance between the two units is necessarily long, and thus it is impossible to effect at a high speed the signal transmission through signal lines between the two units. Therefore, it becomes impossible to perform in a definite machine cycle such a processing as stopping one of the two executing units by an interruption source detected in the other executing unit, and the machine cycle becomes necessarily longer.